Verification Engineer jobs - Sunnyvale, CA
Subscribe to RSS Feed| Posted | Job Title | Company | Location |
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Featured Job Postings from the Web
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| May 29 | Senior Application Software Engineer Job | Akamai Technologies | San Mateo, CA |
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Senior Application Software Engineer Location: US-CA-San Mateo Posted Date: 5/29/2012 Cost ... SL-MY-SASE-0512 Senior Application Software Engineer (Akamai Technologies, Inc.; San... more |
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| May 26 | Engineer, Staff I - IC Design | Broadcom | Sunnyvale, CA |
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and data in handheld devices. Our design verification team supports multiple lines of ... verification testplan - Developing verification environment and test suites for... more |
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| May 24 | Senior Engineer Job | Akamai Technologies | San Mateo, CA |
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Senior Engineer Location: US-CA-San Mateo Posted Date: 5/24/2012 Cost Center: 264 Category ... - Minimum of 2 years of excellent fundamentals in verification techniques such as black /... more |
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| May 16 | IC Design Verification for Mobile Platforms | Broadcom | Sunnyvale, CA |
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and data in handheld devices. Our design verification team supports multiple lines of ... verification testplan - Developing verification environment and test suites for... more |
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| May 16 | Senior SW Development Engineer, Advanced Emulation/Co-Simulation | Cadence Design Systems | San Jose, CA |
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Responsibilities include working on Virtual Verification Machine (VVM or SWIT) and VIP ... EDA/CAD tool development experience or logic design verification experience expected... more |
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| May 15 | senior software engineer | Cadence Design Systems | San Jose, CA |
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next generation of IC manufacturing verification software toools for IC ... Previous experience with IC physical layout design/verification tool development is requir... more |
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| Apr 12 | Technical Marketing Engineer | Cadence Design Systems | San Jose, CA |
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campaigns, etc.) for hardware-assisted verification products * Works closely with ... ASIC/SoC verification process and low power verification is a plus * Attentiveness to... more |
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| Apr 10 | Multimedia Design Verification Engineer | QUALCOMM | Santa Clara, CA |
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CA or Santa Clara, CA As a Verification Engineer, you will be responsible for ... for mobile applications.As a Verification Engineer, you will be responsible for... more |
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| Apr 09 | Staff Verification Engineer-Complex Connectivity Chips | Fabless Semiconductor - Location / Wifi / Bluetooth | Sunnyvale, CA |
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Staff Verification Engineer - Complex Connectivity Chips Position is in Sunnyvale Calif ... are looking for a first class Staff Design Verification Engineer to be part of front end... more |
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| Apr 09 | Senior Verification Methodology Engineer - AMS | Fabless Semiconductor - Location / Wifi / Bluetooth | San Jose, CA |
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applications. We are looking for a Senior Verification Methodology Engineer to work ... The primary job purpose of a Senior Verification Methodology Engineer within R&D... more |
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| Mar 26 | Hardware Validation Engineer | Amazon.com | Cupertino, CA |
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new Kindle Fire. The products we design and engineer are easy-to-use and offer users ... to test the hardware. * Functional verification of electrical subsystems. * In... more |
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| Feb 15 | Sr Design Engineer , Physical Design | Cadence Design Systems | San Jose, CA |
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power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR ... EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM. more |
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| Feb 07 | Sr Application Engineer , Physical IC | Cadence Design Systems | San Jose, CA |
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highly desirable. Good knowledge of Physical Verification tools and rule decks is highly desirable. Exposure to digital P&R is a plus. MUST HAVE CURRENT US WORK AUTHORIZATION... more |
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| Jan 13 | Staff Design Engineer, Physical Design | Cadence Design Systems | San Jose, CA |
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power/signal integrity signoff, physical verification, DRC/LVS /Antenna) EM/IR ... EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM. more |
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| Dec 13 | Sr Design Verification Engr | Cadence Design Systems | San Jose, CA |
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verification environments including advanced verification component development, ... verification, preferably using Metric Driven Verification (MDV) methodologies The... more |
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More Job Postings from the Web
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| May 25 | Senior Staff CPU Verification Engineer | Broadcom | Santa Clara, CA |
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a new architecture/micro-architecture on the verification environment Understand ... knowledge and understanding of different verification methodologies: - architecture vs... more |
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| May 24 | Sr Staff Engineer-Verification | CSR | Sunnyvale, CA |
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knowledge of High-level constrain-random verification using SystemVerilog, SystemC, ... for a first class Design Verification Engineer to be part of front end digital... more |
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| May 22 | ASIC Verification Engineer, Staff | Infinera | Sunnyvale, CA |
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ASIC Verification Engineer, Staff Job Description: * The successful candidate will ... tools; familiarity with evolving verification methodologies. * Very good... more |
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| May 12 | Design Verification Engineer | Apple | Cupertino, CA |
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systems in C/C++/assembly. Familiarity with verification environments, VMM, System ... Clear understanding of constrained random verification process, functional coverage,... more |
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| May 12 | ASIC Verification Engineer | AMD | Sunnyvale, CA |
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Verification Engineer - Graphics We are accepting applications for engineers at all levels ... This position is for a verification engineer in AMD's graphics group working on... more |
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